Effective MIM fabrication method and apparatus to avoid breakdown and leakage on damascene copper process

ABSTRACT

A method and apparatus for forming a metal-insulator-metal device that avoids breakdown and leakage due to semiconductor damascene copper fabrication processes associated with the formation of the metal-insulator-metal device. An extra pattern for forming a metal-insulator-metal device can be defined to remove an outer top electrode area associated with the metal-insulator-metal device. The metal-insulator-metal device can be formed without the outer top electrode area to avoid recesses in an insulator layer thereof and achieve a final metal-insulator-metal device structure that avoids breakdown and leakage as a result of associated damascene copper processes.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductorfabrication techniques and devices thereof. The present invention alsorelates to MIM structures and devices thereof. The present inventionadditionally relates to recesses formed on MIM structures. The presentinvention also relates to methods and devices for avoiding breakdown andleakage in MIM structures. The present invention additionally relates todamascene processes and devices thereof.

BACKGROUND OF THE INVENTION

[0002] Metal-insulator-metal fabrication technology is widely used inthe fabrication of semiconductor integrated circuit devices.Metal-insulator-metal (MIM) capacitors, for example, are commonlyutilized in high performance applications of CMOS technology. A typicalMIM capacitor possesses a sandwich structure that can generally bedescribed as a parallel plate capacitor. The capacitor top metal (CTM)is separated from the capacitor bottom metal (CBM) by a thin insulatinglayer. Both parallel plates are conventionally made from Al or AlCualloys. These metals are patterned and etched needing severalphotolithography photo masking steps. The thin insulating dielectriclayer is usually made from silicon oxide or silicon nitride deposited bychemical vapor deposition (CVD).

[0003] Such MIM capacitors are generally utilized in semiconductordevices, such as integrated circuits (ICs) for storing an electricalcharge. In ICs, such as dynamic random access memory (DRAM), capacitorsare used for storage in the memory cells. Typically, capacitors formedin ICs include a lower electrode made of, e.g., polycrystalline silicon(polysilicon), a dielectric layer made of, e.g., tantalum pentoxideand/or barium strontium titanate, and an upper electrode made of, e.g.,titanium nitride, titanium, tungsten, platinum or polysilicon.

[0004] MIM capacitors can be formed utilizing damascene fabricationtechnology, which well known in the semiconductor fabrication arts. Thedamascene processing is a “standard” method for fabricating planarcopper interconnects. Damascene wiring interconnects (and/or studs) areformed by depositing a dielectric layer on a planar surface, patterningit using photolithography and oxide reactive ion etch (RIE), thenfilling the recesses with conductive metal. The excess metal is removedby chemical mechanical polishing (CMP), while the troughs or channelsremain filled with metal. For example, damascene wiring lines can beused to form bit lines in DRAM devices, with processing similar to theformation of W studs in the logic and DRAM devices. In both examples,sputtered Ti/TiN liners, underlying diffusion barriers, have been coatedwith chemical vapor deposited (CVD) W metal, then polished back tooxide.

[0005] Note generally that the term “damascene process” or “damasceneprocesses” is utilized herein to refer to a standard semiconductorfabrication processes. In the processing sequence known in the art asthe “Damascene Process”, a dielectric layer can be patterned using knowntechniques such as the use of a photoresist material, which is exposedto define the wiring pattern. After developing, the photoresist acts asa mask through which a pattern of the dielectric material is removed bya subtractive etch process such as plasma etching or reactive ionetching. This is generally termed a lithography or photolithographyprocess or operation and may be used for both additive or subtractivemetallization procedures as is known in the art.

[0006] In the dual-damascene process, a monolithic stud/wire structureis formed from the repeated patterning of a single thick oxide filmfollowed by metal filling and CMP. First, a relatively thick oxide layeris deposited on a planar surface. The oxide thickness is slightly largerthan the desired final thickness of the stud and wire, since a smallamount of oxide is removed during CMP. Stud recesses (i.e., recesses)can be formed in the oxide using photolithography and RIE that eitherpartially etches through the oxide or traverses the oxide and stops onthe underlying metal to be contacted. The wire recesses can then beformed using a separate photolithography step and a timed oxide etchingstep. If the former stud RIE option is used, the wire etching completesthe drilling of the stud holes.

[0007] Next, wire metallization layers can be deposited, then planarizedusing CMP. The resulting interconnects are produced with fewer processsteps than with conventional processing and with the dual damasceneprocess, two layer of metal are formed as one, i.e., wiring line andcontact stud vias, avoiding an interface between the layers.

[0008] Another metal deposition technique, besides the aforementionedsputtering techniques, has been adapted as a standard for coppermetallization. This technique is referred to generally as theelectrochemical deposition (ECD) of copper. The electrochemical copperdeposition (ECD) requires, e.g., sputtering techniques, physical vapordeposition (PVD), to deposit thin underlying diffusion barrier film (Ta,TaN) and a conductive “seed” layer of copper.

[0009] One of the primary problems encountered during MIM fabricationprocesses, particular copper damascene processes, involves the formationof recesses or film notches during device fabrication. For example,recesses between TaN and copper interfaces in MIM devices followingcopper CMP can lead easily to MIM breakdown and leakage due to thepresence of such recesses. In an oxide layer of an MIM device, forexample, a recess can lead to breakdown of the oxide layer. The presentinventors have thus concluded based on the foregoing that a need existsfor an apparatus and method which can effectively prevent the formationof such recesses. The present invention disclosed herein addresses thisimportant need.

BRIEF SUMMARY OF THE INVENTION

[0010] The following summary of the invention is provided to facilitatean understanding of some of the innovative features unique to thepresent invention, and is not intended to be a full description. A fullappreciation of the various aspects of the invention can be gained bytaking the entire specification, claims, drawings, and abstract as awhole.

[0011] It is therefore one aspect of the present invention to provide animproved semiconductor fabrication method and apparatus.

[0012] It is yet another aspect of the present invention to provide animproved metal-insulator-metal (MIM) fabrication method and apparatus.

[0013] It is still another aspect of the present invention to provide animproved MIM device structure that avoids breakdowns and leakagesassociated with damascene copper processes.

[0014] It is also an aspect of the present invention to provide an MIMcapacitor which is formed based on an extra pattern in which an outertop electrode area is removed to avoid overlapping of a recessed bottomelectrode area to achieve a final MIM capacitor structure.

[0015] The above and other aspects of the present invention can thus beachieved as is now described. A method and apparatus are disclosedherein for forming a metal-insulator-metal device that avoids breakdownand leakage due to semiconductor damascene copper fabrication processesassociated with the formation of the metal-insulator-metal device. Anextra pattern may be defined for forming a metal-insulator-metal deviceto remove an outer top electrode area associated with themetal-insulator-metal device and avoid recesses in an insulating layerthereof.

[0016] The metal-insulator-metal device is thus generally formed withoutthe outer top electrode area, such that an area previously associatedwith the outer top electrode area overlaps a recessed bottom electrodearea of the metal-insulator-metal device to achieve a finalmetal-insulator-metal device structure that avoids breakdown and leakageas a result of associated damascene copper processes. Essentially, aninitial pattern may be defined for forming the metal-insulator device,and thereafter the extra pattern can be defined.

[0017] The metal-insulator-metal device generally can comprisemetal-insulator-metal capacitor. The metal-insulator-metal device can beformed utilizing at least one TaN layer and at least one copper layer. Afirst TaN layer may be deposited upon a substrate followed by adielectric layer upon the substrate to form the metal-insulator-metaldevice and a second TaN layer to form the metal-insulator-metal device.

[0018] The extra pattern described herein can be generally defined toremove only the outer top electrode area associated with themetal-insulator-metal device. Such an extra pattern can also be definedto remove at least one film notch associated with the formation of themetal-insulator-metal device. Finally, the extra pattern can be definedto remove at least one recess associated with the formation of themetal-insulator-metal device. The extra pattern is thus defined toremove the outer top electrode area only, wherein the area overlaps therecessed bottom electrode area. Formation of the capacitor is thuscontrolled at the area where a recess profile is not included, therebyavoiding MIM structure breakdown and leakage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying figures, in which like reference numerals referto identical or functionally-similar elements throughout the separateviews and which are incorporated in and form part of the specification,further illustrate the present invention and, together with the detaileddescription of the invention, serve to explain the principles of thepresent invention.

[0020]FIG. 1 illustrates a block diagram of a prior art MIM structurewhich is faced with film notch and chemical corrosion issues;

[0021]FIG. 2 depicts a block diagram of an MIM structure that can beformed in accordance with a preferred embodiment of the presentinvention;

[0022]FIG. 3 illustrates a block diagram of an MIM structure that can beformed in accordance with an alternative embodiment of the presentinvention;

[0023]FIG. 4 depicts a high-level flow chart of operations illustratinggeneral operational steps that can be implemented in accordance withpreferred or alternative embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The particular values and configurations discussed in thesenon-limiting examples can be varied and are cited merely to illustrateembodiments of the present invention and are not intended to limit thescope of the invention.

[0025]FIG. 1 illustrates a block diagram of a prior art MIM structure 10which is faced with film notch and chemical corrosion issues. MIMstructure 10 contains a TaN layer 12, which is formed above anintermediate layer 14. Note that intermediate layer 14 may be formed asan oxide or SiN layer. A second TaN layer is located below intermediatelayer 16. A diffusion layer 18 surrounds an internal layer 19, which maybe formed from copper. Diffusion layer 18 can be formed from TaN.

[0026] One of the problems that prior art MIM structures, such as MIMstructure, can encounter is the formation of recesses, such as recesses24, 26, 28, 30, 32, and 24. Such recesses between TaN and copperinterfaces after copper chemical mechanical polishing (CMP) can easilylead to MIM breakdown due to recess formation on the MIM structure. Suchrecesses or notches (i.e., film notches) are illustrated as V-shapedrecesses in FIG. 1. In particular, the intermediate layer 14, which maybe formed from oxide or SiN, can break down.

[0027] Corrosion can occur at recesses 22 and 20 as a result of theformation of MIM structure 10. MIM structure 10 is generally formed as aresult copper damascene processes. Thus, a need exists to avoidbreakdown and leakage in an MIM structure as a result of the formationof V-shaped recesses and/or notches, and associated corrosion thereof.

[0028]FIG. 2 depicts a block diagram of an MIM structure 32 that can beformed in accordance with a preferred embodiment of the presentinvention. Generally, MIM structure 30 is designed to avoid the V-shapedrecesses evident in MIM structure 10 of FIG. 1. An extra pattern may bedefined for forming a MIM structure 34 (i.e., a metal-insulator-metaldevice) to remove an outer top electrode area associated with the MIMstructure and thus remove the V-shaped recesses, as indicated at area32.

[0029] Note that area 32 is generally illustrated as a dashed circle toindicate the face that the V-shaped recess previously indicated in MIMstructure 10 of FIG. 1 is not present in MIM structure 30 of FIG. 2.This also holds true for area 33 of FIG. 2. MIM structure 30 thusincludes a metal layer 34 (i.e., M), an insulator layer 35 (i.e., I),and a metal layer 38 (i.e., M). Hence, layers 34, 36, and 38 generallyform an MIM structure. MIM structure 30 also is associated with aninternal copper layer 42 and a diffusion layer 40, which can be formedfrom TaN.

[0030] Layer 34 can be formed from TaN, while layer 36 can be formedfrom oxide or SiN. Additionally, layer 38 can be formed from TaN. Notethat recesses 50, 52 and 54, 56 are present in MIM structure 30,however, such recesses or film notches do not pose a problem becauserecesses formed in the metal layer are sufficient to permit a flow ofcurrent that would otherwise breakdown if such recesses were present inan oxide or SiN layer. Thus, such recesses are not present in layer 36(i.e., oxide or SiN).

[0031]FIG. 3 illustrates a block diagram of an MIM structure 60 that canbe formed in accordance with an alternative embodiment of the presentinvention. Extra patterns can also be defined to avoid the formation ofrecesses in the oxide or SiN layer of an MIM structure. FIG. 3 thusillustrates layers 63, 64, and 65 which respectively metal, insulator,and metal layers. However, notches or V-shaped recesses are not presentin layer 64 in particular, which can comprise an oxide or SiN layer.Thus, the flow of current will not cause breakdown, as is the case withthe configuration depicted in FIG. 1. MIM structure 60 also generallyincludes an inner copper layer 69, recesses 71, 72, and a diffusionlayer 68, which may be formed from TaN. Recesses are thus avoided in aninsulating layer 64 of MIM structure 60.

[0032]FIG. 4 depicts a high-level flow chart 80 of operationsillustrating general operational steps that can be implemented inaccordance with preferred or alternative embodiments of the presentinvention. Initially, in the formation of an MIM structure utilizingcopper damascene fabrication processes, a copper chemical mechanicalpolishing (CMP) operation can occur, as indicated at block 82. Notegenerally that chemical mechanical polishing is one accepted method ofplanarization. This planarization method typically requires that thesubstrate be mounted on a carrier or polishing head, with the surface ofthe substrate to be polished exposed.

[0033] The substrate is then placed against a rotating polishing pad. Inaddition, the carrier head may rotate to provide additional motionbetween the substrate and polishing surface. Further, a polishingslurry, including an abrasive and at least one chemically-reactiveagent, may be spread on the polishing pad to provide an abrasivechemical solution at the interface between the pad and substrate.Important factors in the chemical mechanical polishing process are: thefinish (roughness) and flatness (lack of large scale topography) of thesubstrate surface, and the polishing rate. Inadequate flatness andfinish can produce substrate defects. The polishing rate sets the timeneeded to polish a layer. Thus, it sets the maximum throughput of thepolishing apparatus.

[0034] Each polishing pad provides a surface, which, in combination withthe specific slurry mixture, can provide specific polishingcharacteristics. Thus, for any material being polished, the pad andslurry combination is theoretically capable of providing a specifiedfinish and flatness on the polished surface. The pad and slurrycombination can provide this finish and flatness in a specifiedpolishing time. Additional factors, such as the relative speed betweenthe substrate and pad, and the force pressing the substrate against thepad, affect the polishing rate, finish and flatness.

[0035] Following the performance of a CMP operation, as indicate atblock 82, a TaN/dielectric/TaN deposition operation can occur, asdepicted at block 84. TaN is deposited on a substrate, followed by adielectric layer, and thereafter by another TaN layer. As indicated atblock 86, a pattern may generally be defined to form the MIM structure.

[0036] Thereafter, as depicted at block 88, an extra pattern may bedefined. Such an extra pattern is defined, as indicated at block 90, toremove an outer top electrode area only, such that this area previouslyoverlapped a recessed bottom electrode. Thus, such a pattern avoids theformation of recesses or film notches in the dielectric area. Multipleextra patterns can be defined to avoid the formation of additionalrecesses. The result of the use of such extra patterns is the avoidanceof breakdown or leakage, as indicated at block 92.

[0037] Based on the foregoing, it can be appreciated that the presentinvention discloses a method and apparatus for forming ametal-insulator-metal device that avoids breakdown and leakage due tosemiconductor damascene copper fabrication processes associated with theformation of the metal-insulator-metal device. An extra pattern may bedefined for forming a metal-insulator-metal device to remove an outertop electrode area associated with the metal-insulator-metal device.

[0038] The metal-insulator-metal device is thus generally formed withoutthe outer top electrode area, such that an area previously associatedwith the outer top electrode area overlaps a recessed bottom electrodearea of the metal-insulator-metal device to achieve a finalmetal-insulator-metal device structure that avoids breakdown and leakageas a result of associated damascene copper processes. Essentially, aninitial pattern may be defined for forming the metal-insulator device,and thereafter the extra pattern can be defined.

[0039] The metal-insulator-metal device generally can comprisemetal-insulator-metal capacitor. The metal-insulator-metal device can beformed utilizing at least one TaN layer and at least one copper layer. Afirst TaN layer may be deposited upon a substrate followed by adielectric layer upon the substrate to form the metal-insulator-metaldevice and a second TaN layer to form the metal-insulator-metal device.

[0040] The extra pattern is generally defined to remove only the outertop electrode area associated with the metal-insulator-metal device. Theextra pattern can also be defined to remove at least one film notchassociated with the formation of the metal-insulator-metal device.Finally, the extra pattern can be defined to remove at least one recessassociated with the formation of the metal-insulator-metal device.

[0041] The extra pattern is thus defined to remove the outer topelectrode area only, wherein the area overlaps the recessed bottomelectrode area. Formation of the capacitor is thus controlled at thearea where a recess profile is not included, thereby avoiding MIMstructure breakdown and leakage. Thus, the formation of recesses in aninsulating layer of an MIM structure are effectively avoiding throughthe use of an extra pattern as explained herein. In particular, suchrecesses or film notches can be avoided in the insulating oxide or SiNlayer of an MIM structure through the use of such an extra pattern forremoving the outer top electrode area only.

[0042] The embodiments and examples set forth herein are presented tobest explain the present invention and its practical application and tothereby enable those skilled in the art to make and utilize theinvention. Those skilled in the art, however, will recognize that theforegoing description and examples have been presented for the purposeof illustration and example only. Other variations and modifications ofthe present invention will be apparent to those of skill in the art, andit is the intent of the appended claims that such variations andmodifications be covered. The description as set forth is thus notintended to be exhaustive or to limit the scope of the invention. Manymodifications and variations are possible in light of the, aboveteaching without departing from scope of the following claims. It iscontemplated that the use of the present invention can involvecomponents having different characteristics. It is intended that thescope of the present invention be defined by the claims appended hereto,giving full cognizance to equivalents in all respects.

1. A method for forming a metal-insulator-metal device that avoidsbreakdown and leakage due to semiconductor damascene copper fabricationprocesses associated with the formation of said metal-insulator-metaldevice, said method comprising the steps of: defining an extra patternfor forming a metal-insulator-metal device to remove an outer topelectrode area associated with said metal-insulator-metal device; andforming said metal-insulator-metal device without said outer topelectrode area to avoid recesses in an insulating layer thereof andachieve a final metal-insulator-metal device structure that avoidsbreakdown and leakage as a result of associated damascene copperprocesses.
 2. The method of claim 1 further comprising the steps of:defining an initial pattern for forming said metal-insulator device; andthereafter defining said extra pattern.
 3. The method of claim 1 furthercomprising the step of: forming said metal-insulator-metal device,wherein said metal-insulator-metal device comprisesmetal-insulator-metal capacitor.
 4. The method of claim 1 furthercomprising the step of: forming said metal-insulator-metal deviceutilizing at least one TaN layer.
 5. The method of claim 1 furthercomprising the step of: forming said metal-insulator-metal deviceutilizing at least one copper layer.
 6. The method of claim 1 furthercomprising the step of: forming said metal-insulator-metal deviceutilizing at least two TaN layers.
 7. The method of claim 1 furthercomprising the steps of: depositing a first TaN layer upon a substrateto form said metal-insulator-metal device; thereafter depositing adielectric layer upon said substrate to form said metal-insulator-metaldevice; and thereafter depositing a copper layer upon said substrate toform said metal-insulator-metal device.
 8. The method of claim 1 whereinthe step of defining an extra pattern for forming ametal-insulator-metal device to remove an outer top electrode areaassociated with said metal-insulator-metal device, further comprises thestep of: defining at least one extra pattern to remove only said outertop electrode area associated with said metal-insulator-metal device. 9.The method of claim 1 wherein the step of defining an extra pattern forforming a metal-insulator-metal device to remove an outer top electrodearea associated with said metal-insulator-metal device, furthercomprises the step of: defining said extra pattern to remove at leastone film notch associated with the formation of saidmetal-insulator-metal device.
 10. The method of claim 1 wherein the stepof wherein the step of defining an extra pattern for forming ametal-insulator-metal device to remove an outer top electrode areaassociated with said metal-insulator-metal device, further comprises thestep of: defining said extra pattern to remove at least one recessassociated with the formation of said metal-insulator-metal device. 11.An apparatus for forming a metal-insulator-metal device that avoidsbreakdown and leakage due to semiconductor damascene copper fabricationprocesses associated with the formation of said metal-insulator-metaldevice, said apparatus comprising: an extra pattern defined for forminga metal-insulator-metal device to remove an outer top electrode areaassociated with said metal-insulator-metal device; and wherein saidmetal-insulator-metal device is formed without said outer top electrodearea to avoid recesses formed in an insulating layer of saidmetal-insulator device to achieve a final metal-insulator-metal devicestructure that avoids breakdown and leakage as a result of associateddamascene copper processes.
 12. The apparatus of claim 11 furthercomprising: an initial pattern defined for forming said metal-insulatordevice, wherein said initial pattern is defined prior to said extrapattern.
 13. The apparatus of claim 11 wherein saidmetal-insulator-metal device comprises metal-insulator-metal capacitor.14. The apparatus of claim 11 wherein said metal-insulator-metal deviceis formed utilizing at least one TaN layer.
 15. The apparatus of claim11 wherein said metal-insulator-metal device is formed utilizing atleast one copper layer.
 16. The apparatus of claim 11 wherein saidmetal-insulator-metal device is formed utilizing at least two TaNlayers.
 17. The apparatus of claim 11 further comprising: a first TaNlayer deposited upon a substrate to form said metal-insulator-metaldevice; a dielectric layer deposited upon said substrate to form saidmetal-insulator-metal device; and a copper layer deposited on saidsubstrate to form said metal-insulator-metal device.
 18. The apparatusof claim 11 wherein said extra pattern is defined to remove only saidouter top electrode area associated with said metal-insulator-metaldevice.
 19. The apparatus of claim 11 wherein said extra pattern isdefined to remove at least one film notch associated with the formationof said metal-insulator-metal device.
 20. The apparatus of claim 11wherein said extra pattern is defined to remove at least one recessassociated with the formation of said metal-insulator-metal device.